-------- Original-Nachricht --------
Datum: Wed, 12 Oct 2011 14:05:48 -0500
Von: Derek Hower <[email protected]>
An: gem5 users mailing list <[email protected]>
Betreff: Re: [gem5-users] A memory Controller Question
To be a little more clear, a directory controller is something
different than a memory controller in Ruby, but practically speaking
you can think of them as one because in all current cases a directory
controller "owns" a memory controller. Directory controllers are the
coherence engines out at DRAM, while the memory controllers are the
low-level objects that actually do the DRAM accesses at the request of
a directory controller (i.e., they model DDR2). For your purposes,
what Korey said is correct: just use as many directory controllers as
you want memory controllers.
-Derek
On Wed, Oct 12, 2011 at 1:52 PM, Korey Sewell <[email protected]> wrote:
> In Ruby,
> directory controller = memory controller.
>
> It's a bit of a misnomer unfortunately.
>
> On Wed, Oct 12, 2011 at 2:46 PM, LI Zhongqi <[email protected]>
> wrote:
>>
>> Hi,
>>
>> We are trying to model a multiple memory controllers system. When I
>> look inside the interconnect, I found
>>
>> http://gem5.org/File:Interconnection_network.jpg
>>
>> which implies there should be memory controllers connecting to the
>> interconnect.
>>
>> However, from Mesh.py, I only find the L1 and L2 Cache Controllers,
>> DMA Controllers and Directory Controllers connecting to the
>> interconnect. I didn't see any memory controller is explicitly
>> connected to the interconnect. We are using MOESI_Directory_CMP
>> protocol.
>>
>> Any clue that how I could implement multiple memory controllers?
>>
>> Basically I think my question is: as long as there is no explicit
>> memory controller in the interconnect, which component actually
>> supplies the off-chip memory data? Is it the directory controller?
>> Thank you!
>>
>> --
>> Best regards,
>>
>> =================
>> Zhongqi Li
>> _______________________________________________
>> gem5-users mailing list
>> [email protected]
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
>
> --
> - Korey
>
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>
Hi Derek,
can you say a littelbit more about the differences between directory-
and memory-controller?
I want to implement a new kind of hierarchic mainmemory.
My idea is to have to stages. First a small common DRAM, and behind
this a very large but slow other Memory like a flashram or something
like that. The DRAM should be transparent for the CPU, so it just read
from the DRAM and if it the data is not in the DRAM, the Controller
pull the data from the second lvl with LRU or so.
Are there some differences between directorz and memory-controller for me?
When it is to deep, just say it, than i open a new question in dev/user.
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