Hi Tejasi,
In general there is *no fixed rule* for these, and depends on the
coherence protocol.
For most protocols currently in gem5, each "Directory" Controller
implies both a Directory (i.e. state) and a Memory Controller.
The memory controller models the delay to main memory. We don't define
and connect a memory module separately as far as I know.
The number of directories is an independent parameter defined from
command line (--num-dirs).
If you take a look at configs/ruby/MOESI_CMP_directory.py,
you can see that it creates L1 controllers, L2 controllers and Directory
Controllers (in which it creates both a DirectoryMemory => state, and a
memory controller).
Now when the directory receives a request that is not currently on-chip
(indicated by directory state), it sends the request to the memory
controller which models memory delay for reads/writes etc ... [done in
the protocol's .sm file].
In terms of connections, all controllers (L1, L2 and Directory) can be
connected in any manner.
We provide two mesh topologies: Mesh.py and MeshDirCorners.py.
Both topologies create a Mesh with the number of routers = number of
cpus (=number of L1s).
Mesh.py assumes equal number of all controllers (L1, L2 and directory),
and connects one L1, one L2 (if it exists) and one directory to each
network router.
MeshDirCorners.py assumes 4 directories and connects them at each corner.
All DMA controllers are just connected to router 0 (arbitrary decision)
I think.
You can design your own topology too using the given ones as reference.
You just need to add a .py file of your topology in the topologies
folder, and also add it in
src/mem/ruby/network/topologies/SConscript
Hope this helps,
Tushar
On 10/27/2011 4:09 PM, tejasi pimpalkhute wrote:
Hi,
I was looking into the code file Mesh.py in Topology folder and the
online documentation for it says that every node has L1,L2 cache and
directories connected to it. As I had read somewhere, in Gem5,
directory controller and memory controller are same, could you please
let me know if Directory connected to each node is same as main
memory? Also, it seems that DMA controller is attached to only
remainder nodes as per the code. So, it is a little bit confusing.
Could you please elaborate the connections of nodes to memory
controller and main memory.
Thanks!
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