If L2 has BLK and reply that to L1, then there is no need to mark BLK in L2 as "prefetched". However I am talking about MM->L2->L1.
Since L1 issued address 'X' (and wanted BLK) and L2 can not reply that, I think all cache levels should mark BLK as "prefetched" On 2/10/12, biswabandan panda <biswa....@gmail.com> wrote: > thats not true. You can fiind prefetched blocks at L2 also. > > On Fri, Feb 10, 2012 at 1:13 PM, Mahmood Naderan > <mahmood...@gmail.com>wrote: > >> Dear all, >> Assume the prefetcher is enabled for L1 and L2. When L1 issue 'X', it >> checks L2 for that address. Also assume that L2 misses. MM replies to >> L2 with a BLK containing 'X'. Then L2 replies to L1 and pass BLK. >> >> While debugging, I noticed that BLK is set to "prefetched" only in L1. >> In another word, L2 treats BLK as a regular block. >> >> Is this implementation correct? I think that BLK should be marked as >> "prefetched" in L2 too. >> >> Do you have any comment? >> -- >> // Naderan *Mahmood; >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > -- > > *thanks®ards > * > *BISWABANDAN* > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
