What do you mean by synchronizing the memory access? The mfence microop is
being used to make the other processors aware of the stores carried out by
a certain processor. Lock instruction guarantees that the memory location
is read and modified atomically. We can make ldstl and stul also act as
mfence, but for that the O3 CPU itself would need to change. There have
been some discussion on this in the months of October and November last
year. You can go through the archieves of the gem5-dev mailing list to
read more about it.
--
Nilay
On Fri, 24 Feb 2012, [email protected] wrote:
Hi Nilay,
Thank you for your replying. Suppose gem5 simulates a two cores
system, each of cores have its own O3 CPU. if system runs following
instructions:
suppose the data of [eax] is 0x0
lock inc [eax] --- Core 0, first run
lock add [eax], 0x2 --- Core 1, second run
expected result is 0x3, should not 0x2 or 0x1
Does the mfence uop can synchronize the memory access? Or this
semantics is guaranteed by the "Request::Lock" flag, while the mfence only
synchronize the instructions in the same core? Further, can we merge the
"mfence" uop function to the ldstl and stul? I think it's easy because we
only need add a "MemBarrier" flag to these uop.
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