Thanks for the reply Nilay, I looked at the cache_imple.hh briefly but I seem to be more confused by it.
Also, I have a question regarding functional WriteReq. It seems like these request access main memory in the trace file but it doesn't show up in the system.physmem.num_writes. I've read the wiki about the type of accesses, so is it correct in sayin that these request are somethin that the simulator does to load binaries etc but are not the accesses generated by the program that we're simulating? thanks in advance! On 2012-03-01, at 12:21 PM, Nilay Vaish <[email protected]> wrote: > On Thu, 1 Mar 2012, [email protected] wrote: > >> Hi Everyone, >> >> I've read some documentation and past archives and I understand that in the >> classic memory model, gem5 uses the MOESI snooping protocol and I also >> understand that this is always enabled even if there is only ONE core. >> >> I am running some benchmarks and trying to figure out the number of last >> level cache misses (read + writebacks) to main memory. Looking at the >> Stats.txt file, I observed that there are two parameters related to >> writebacks: >> >> 1) system.l2.Writeback_access >> 2) system.l2.writebacks >> >> I noticed that the 2nd parameters actually matches up with the num_writes to >> physical memory, so I assume that this is the actual number of writebacks >> from last level cache to main memory. >> >> However, I am not sure what the 1st parameter is. Is it something to do with >> the cache coherency being enabled in a single core? I've read this archive >> (http://www.mail-archive.com/[email protected]/msg03250.html) and Steve >> mentioned that the 1st parameter is the writeback requests received by the >> cache. What is that mean exactly? >> >> Thank You >> Zheng Wu >> > > I would suggest that you look at the relevant source files in src/mem/cache > directory. You can always negelect stats that you don't understand, and add > your own. > > -- > Nilay > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
