Hi,
As directed in the previous email, I created the L3 cache and connected it
using a new bus tol3bus to the L2s and membus to memory. However, when I
see the stats, I see no activity across the tol3bus and membus. Is there
any other setup needed? Below are relevant line from CacheConfig.py file:
if options.l3cache:
system.l3 = L3Cache(size = options.l3_size, assoc =
options.l3_assoc,
block_size=options.cacheline_size)
system.tol3bus = Bus()
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
.....
system.cpu[i].l2 = L2Cache(size = options.l2_size, assoc =
options.l2_assoc,
block_size=options.cacheline_size)
system.cpu[i].tol2bus = Bus()
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
.......
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
system.cpu[i].createInterruptController()
system.cpu[i].connectAllPorts(system.cpu[i].tol2bus,
system.membus)
Am I missing something ?
Thanks for your help !
Regards,
Ankita
On Sat, Feb 25, 2012 at 6:51 PM, Ankita (Garg) Goel <[email protected]>wrote:
> Thanks Nilay and Steve, that was useful !
>
>
> On Sat, Feb 25, 2012 at 12:07 PM, Steve Reinhardt <[email protected]>wrote:
>
>> If you're not using Ruby though, it should be pretty straightforward...
>> you just need to create a new cache between the L2(s) and the main memory,
>> along with a new bus. For example, the membus would now go between the L3
>> and memory, and you'd need to create a new "tol3bus" that goes between the
>> L2(s) and L3.
>>
>> Steve
>>
>>
>> On Fri, Feb 24, 2012 at 2:42 PM, Nilay Vaish <[email protected]> wrote:
>>
>>> If you are using Ruby, you have to have a three level protocol to have a
>>> three level cache hierarchy.
>>>
>>> --
>>> Nilay
>>>
>>>
>>> On Fri, 24 Feb 2012, Ankita (Garg) Goel wrote:
>>>
>>> Hi,
>>>>
>>>> If I want to just simulate private L1 and L2 caches and a shared L3,
>>>> then
>>>> the coherence protocol would still be 2-level, just between L2 and L3.
>>>> So
>>>> do you think just modifying the config script to create an L3 cache,
>>>> connecting it to the right ports, etc would work ?
>>>>
>>>> Regards,
>>>> Ankita
>>>>
>>>> On Wed, Feb 8, 2012 at 10:53 AM, Nilay Vaish <[email protected]> wrote:
>>>>
>>>> Right, L3 is not supported as of now. There is no three level protocol
>>>>> available.
>>>>>
>>>>>
>>>>> On Wed, 8 Feb 2012, Simon Hammond wrote:
>>>>>
>>>>> Thanks Nilay,
>>>>>
>>>>>>
>>>>>> So does that mean at present L3 is not supported ("as-is") if we are
>>>>>> using Ruby as well?
>>>>>>
>>>>>>
>>>>>> S.
>>>>>>
>>>>>> On Feb 8, 2012, at 9:29 AM, Nilay Vaish wrote:
>>>>>>
>>>>>> Are you using Ruby? If yes, then you will have to write a three level
>>>>>>
>>>>>>> coherence protocol first.
>>>>>>>
>>>>>>> --
>>>>>>> Nilay
>>>>>>>
>>>>>>> On Wed, 8 Feb 2012, Simon Hammond wrote:
>>>>>>>
>>>>>>> Hey guys,
>>>>>>>
>>>>>>>>
>>>>>>>> Can you tell me how I can configure a simulation to use a L3 cache?
>>>>>>>>
>>>>>>>> I have taken a look in the simulation scripts provided and the CPU
>>>>>>>> objects but there does not seem to be any reference to an L3 cache
>>>>>>>> (ports
>>>>>>>> etc). I'm probably missing something here.
>>>>>>>>
>>>>>>>> Thank you.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> Simon Hammond
>>>>>>>>
>>>>>>>> 1-(505)-845-7897 / MS-1319
>>>>>>>> Scalable Computer Architectures / CSRI
>>>>>>>> Sandia National Laboratories, NM
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> ______________________________****_________________
>>>>>>>>
>>>>>>> gem5-users mailing list
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>>>>>>> >
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>> Simon Hammond
>>>>>>
>>>>>> 1-(505)-845-7897 / MS-1319
>>>>>> Scalable Computer Architectures / CSRI
>>>>>> Sandia National Laboratories, NM
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> ______________________________****_________________
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>>>>>> >
>>>>>>
>>>>>> ______________________________****_________________
>>>>>>
>>>>> gem5-users mailing list
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>>>>> http://m5sim.org/cgi-bin/****mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users>
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>>>>> >
>>>>>
>>>>>
>>>>
>>>>
>>>> --
>>>> Regards,
>>>> Ankita
>>>>
>>>> ______________________________**_________________
>>> gem5-users mailing list
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>>
>>
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>
>
>
> --
> Regards,
> Ankita
>
>
>
--
Regards,
Ankita
Graduate Student
Department of Computer Science
University of Texas at Austin
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