Hi, I find that in cache_impl.hh, when a cache receives a read request, it would forward to upper level caches to check if they want to handle it. But I see the memInhibit flag is not forwarded. (not copied from original packet to the forwarded packet)
In my simulation, L2 of core 0 sends out a read request. L2 of core 1 process it and set memInhibit flag. L2 of core 2 forward the request to L1s of core2, but the forwarded request has memInhibit flag not set. L1s of core2 respond the request again. Such problem triggers the assert in cache_impl.hh. Could any one help me how should I change to avoid the problem? Thanks, chao _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
