Ali, Thanks for the pointers. The issues you pointed out about the cache are on my to-do list. It seems like I need to dig into codes to work around them.
Since I am new to Gem5, I first plan to find a way to migrate the code between the two different cpus (O3 and functional types), and then I will take care of keeping cache states. For migrating the code between the two different cpus, I noticed that people use switchCpus function and this function itself calls switchOut and takeOverFrom functions. As far as I understood, switchOut deschedule events and squashes tick events. It also clears the architectated state of the "old cpu" like branch prediction state, LDST queue, and so on. Since I want to keep the state of my O3 cpu (and I don't want to clear architected state), I was thinking of modifying these two functions to keep the architected state of O3 and call these two functions when the program on O3 reaches a custom pseudo instruction (like "switchToFunctional" instruction). I am not sure this is a correct way to handle it? Any advice or comments would be appreciated. Amin On Sun, May 6, 2012 at 11:06 AM, Ali Saidi <[email protected]> wrote: > Hi Amin, > > If you don't change the state of the cache, writes in the functional state > won't update values in the cache which will cause problems. Similarly, if > you disconnect the caches from the system any dirty data in there won't get > picked up by the functional cpu which would be a problem. To do this you're > going to have to modify the caches to take both those issues into account. > It might be better to have two memory hierarchies. Have one of them > sleeping (but still receiving coherence messages) and then migrate your > code between the two different cpus. > > Ali > > > > On May 2, 2012, at 11:14 AM, Amin Farmahini wrote: > > > Hi All, > > > > I am using O3 CPU for running some benchmarks and am trying to switch > back and forth between functional and detailed modes. When the O3 CPU sees > a defined pseudo instruction (lets call it "switchToFunctional"), it should > switch to a fully "functional mode" and it then again switches back to > detailed mode when the processor sees another defined pseudo instruction > (lets call it "switchToDetailed"). In functional mode, all instructions > should be executed in zero (or fixed) cycles and should NOT change the > architected state of the O3 CPU and cache. In other words, in functional > mode I am only interested in the functional correctness of my program > regardless of timing or any effects on cpu and cache state. Can someone > comment on how to implement this? > > > > I took a look at the "Sampling" page on the Wiki and discussions about > switchCpu instruction on this mailing list. But I am not sure this is in > the right direction. > > > > Thanks, > > Amin > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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