Functional accesses are really intended for debugging, preloading data into the memory system, and other things like that. They're not intended to support a CPU model. Why are you trying to do that? There's no real advantage of using them over atomic accesses.
Steve On Wed, May 16, 2012 at 7:58 PM, Amin Farmahini <[email protected]> wrote: > Hi, > > I am trying to write a cpu model that is very similar to AtomicSimple, but > does Functional memory accesses instead of Atomic accesses. So I defined a > FunctionalCPUPort class for icachePort and dcachePort and used the > sendFunctional(&packet) method to send packets through cache ports (instead > of sendAtomic(&packet)). TLB accesses are all functional as well. I ran a > hello world program to test it. It works fine until it reaches a > storeCondReq memory access. It gives me an assertion failure right after > returning from dcachePort.sendFunctional(&packet). the command for the > packet is MemCmd::StoreCondReq. > > Here is the assertion failure: > gem5.debug: build/ARM/mem/request.hh:437: uint64_t Request::getExtraData() > const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed. > > I can see that loadlink request to the same address completes fine. That > loadlink request happens just a few cycles before this store conditional. > The same hello world program works without any problem on the AtomicSimple > cpu. > Any idea why functional accesses of store conditional do not work? > > configuration: ARM, SE, l2 caches > > Thanks, > Amin > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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