I was able to fix this by adding a few lines to mem/abstract_mem.cc . The new code tracks the address of loadlocked packets and checks the address list when a write occurs. This is similar to atomic access. My hello world program now runs fine, but I'll do more tests later. Thanks for your help.
Steve, You are right about getting a lock by "zero cycle" core that's already held by a O3 core. This case should not happen in my programs. Thanks, Amin On Thu, May 17, 2012 at 8:16 AM, Steve Reinhardt <[email protected]> wrote: > Apparently functional accesses don't support load locked/store > conditional. You could try to add that in, but you might have bigger > problems if you're doing those operations in your "zero cycle" core. What > happens if the code you're running on your "zero cycle" core needs to > acquire a lock that's already held by a regular core? > > Or in other words, there may be fundamental problems with doing > synchronization operations in functional mode, and simply implementing > store conditional might be papering over some deeper issues. > > Steve > > > On Thu, May 17, 2012 at 12:48 AM, Andreas Hansson <[email protected] > > wrote: > >> Without getting into the discussion of the underlying reason for doing >> this, I would imagine that you could create a DebugCPU much like the >> CheckerCPU and use functional read/write, but then I’d also suggest you >> remove any caches for these CPUs. Fundamentally it should work...but as >> Steve already pointed out, this is not at all what the send/recvFunctional >> is intended for.**** >> >> ** ** >> >> Andreas**** >> >> ** ** >> >> *From:* [email protected] [mailto:[email protected]] >> *On Behalf Of *Amin Farmahini >> *Sent:* 17 May 2012 06:17 >> *To:* gem5 users mailing list >> *Subject:* Re: [gem5-users] Store Conditional fails using Functional >> accesses on ARM SE**** >> >> ** ** >> >> I intend to have a couple of O3 cores and a couple of Functional cores in >> one system. a Functional core is supposed to execute one instruction every >> cycle regardless of cache access latency. In this regard, it is somehow >> similar to AtomicSimple. Anyways, since Timing and Atomic accesses cannot >> coexist, I was thinking of using Functional access for the functional core. >> If you can think of another approach, I would be glad to know. >> >> Thanks, >> Amin >> >> PS: My final plan is to have a functional core that is able to execute a >> piece of code (assigned to it by O3) in zero cycle. So the functional core >> is idle most of times, but it is woken up by O3 to run a piece of code that >> should not change the architected state of O3.**** >> >> On Wed, May 16, 2012 at 10:48 PM, Steve Reinhardt <[email protected]> >> wrote:**** >> >> Functional accesses are really intended for debugging, preloading data >> into the memory system, and other things like that. They're not intended >> to support a CPU model. Why are you trying to do that? There's no real >> advantage of using them over atomic accesses.**** >> >> ** ** >> >> Steve**** >> >> ** ** >> >> On Wed, May 16, 2012 at 7:58 PM, Amin Farmahini <[email protected]> >> wrote:**** >> >> Hi, >> >> I am trying to write a cpu model that is very similar to AtomicSimple, >> but does Functional memory accesses instead of Atomic accesses. So I >> defined a FunctionalCPUPort class for icachePort and dcachePort and used >> the sendFunctional(&packet) method to send packets through cache ports >> (instead of sendAtomic(&packet)). TLB accesses are all functional as well. >> I ran a hello world program to test it. It works fine until it reaches a >> storeCondReq memory access. It gives me an assertion failure right after >> returning from dcachePort.sendFunctional(&packet). the command for the >> packet is MemCmd::StoreCondReq. >> >> Here is the assertion failure: >> gem5.debug: build/ARM/mem/request.hh:437: uint64_t >> Request::getExtraData() const: Assertion >> `privateFlags.isSet(VALID_EXTRA_DATA)' failed. >> >> I can see that loadlink request to the same address completes fine. That >> loadlink request happens just a few cycles before this store conditional. >> The same hello world program works without any problem on the >> AtomicSimple cpu. >> Any idea why functional accesses of store conditional do not work? >> >> configuration: ARM, SE, l2 caches >> >> Thanks, >> Amin**** >> >> ** ** >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users**** >> >> ** ** >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users**** >> >> ** ** >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
