OK thank you. On May 30, 2012 9:08 PM, "Nilay" <[email protected]> wrote:
> > On Wed, May 30, 2012 7:54 am, mihai pricopi wrote: > > Please correct me if I'm wrong but from what I understand from the > > documentation the interconnection network is tiled fashioned. That means > > each L2$ bank/tile has a node in the network which corresponds to the > L1$. > > For a mash topology the number of nodes must be equal with the number of > > cores. My concern is that you cannot actually decide the LLC cache into > > multiple banks (e.g. 256) and then use garnet to interconnect them. Is > > this > > true? > > No, this is not true. It is possible to re-write the mesh topology to > support any number of L2 cache banks, irrespective of the number of cores > in the system. > > -- > Nilay > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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