Since I can't see the terminal output, my assumption is that everything is running fine. The warnings and such are all expected/known. On my setup, using the Bbench images for Android Gingerbread and ICS, gem5.opt boots in about 30 minutes - 1 hour, your mileage may vary. You aren't running a benchmark from your command line, so I will assume either 1) nothing is wrong, the machine is booted - vnc or m5term to see or 2) something is wrong with your disk image and it hangs during the boot. I am inclined to think #1.
-- Ray Sent from my iPhone On Jun 12, 2012, at 4:53 PM, Bojun Ma <[email protected]> wrote: > Hi,all > I met some trouble in ARM_FS mode. > When I run a test simulation follow wiki document > build/ARM_FS/gem5.opt -d /tmp/output configs/example/fs.py > > It shows like this: > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled May 30 2012 22:43:45 > gem5 started Jun 11 2012 18:58:36 > gem5 executing on bojun-desktop > command line: build/ARM_FS/gem5.opt -d /tmp/output configs/example/fs.py > Global frequency set at 1000000000000 ticks per second > info: kernel located at: > /home/bojun/GEM5/gem5-stable-549b72de8f72/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 > info: Using bootloader at address 0x80000000 > Listening for system connection on port 5901 > Listening for system connection on port 3456 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > warn: The clidr register always reports 0 caches. > warn: clidr LoUIS field of 0b001 to match current ARM implementations. > warn: The csselr register isn't implemented. > warn: The ccsidr register isn't implemented and always reads as 0. > warn: instruction 'mcr bpiallis' unimplemented > warn: instruction 'mcr icialluis' unimplemented > warn: instruction 'mcr dccimvac' unimplemented > warn: instruction 'mcr dccmvau' unimplemented > warn: instruction 'mcr icimvau' unimplemented > warn: LCD dual screen mode not supported > warn: Returning thumbEE disabled for now since we don't support CP14config > registers and jumping to ThumbEE vectors > warn: instruction 'mcr icialluis' unimplemented > warn: instruction 'mcr bpiallis' unimplemented > > And it seems hang on it forever(over 24 hours). I try to use midterm, but can > not figure out what problem is this. > I really need some help. > Thanks in advance. > > > ---------- Forwarded message ---------- > From: Bojun Ma <[email protected]> > Date: Mon, Jun 11, 2012 at 5:44 PM > Subject: Questions about running SPEC benchmarks in FS mode > To: gem5 users mailing list <[email protected]> > > > Hi,all > I need to run SPEC CPU2000 in FS mode with multi cores system(4 cores at > this moment). I choose ARM_FS. From the document from wiki, I downloaded: > > ARM New Full System Files -- Pre-compiled Linux kernel, and file systems, > and kernel config files. This includes both a cut-down linux and a full > ubuntu linux > > Put it under the main directory of gem5. > > I also created a new bigger disk image following the > http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System > > > I am confused about the steps to running SPEC in FS mode. > > From my understanding of Running SPEC in ARM_FS mode, I need > 1. copy all arm binaries of SPEC 2000 benchmarks and the input set to > the disk image. > > Question: Is there any requirement for the SPEC directory structure I > need to create in disk image? > > 2.Enable smp support > > Question: how to realize smp support? > > 3. "build the boot loader in system/arm and place it somewhere gem5 can > find it." > > Question: I saw this from a previous topic" ARM MP FS" in gem5 mail > list, however I am not quite clear of what does it really mean. > > In system/arm , there is a sub directory > "simple_bootloader", what is the function of this? Can I use it directly > instead of building a new boot loader? > > 4.Command line: > build/ARM_FS/gem5.opt configs/example/fs.py -n NUM_CPUS --script= > runscript.rcs --detailed --caches > > I think I should include the simulation information like which > benchmark to running and which input file to use in the .rcs file, is that > right? > Is there any reference and guide about how to write the runscript.rcs > file for SPEC benchmark in FS mode? > If the command line I mentioned is wrong, what should be the right > command line for running SPEC benchmark in FS mode? > > 5. There is a directory "boot" under gem5/configs. It included several > .rcs file. Is it for FS mode simulation? What is the function of them? > > > > Thanks in advance. > Any suggestion for running SPEC benchmark in FS mode is appreciated. > > > Bojun Ma > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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