Hi Andrea,
Yes that sounds like a bug. All threads need to share a zero reg, or the zero
reg needs to be checked for each thread. I'm curious how that worked with
alpha.
Thanks,
Ali
Sent from my ARM powered mobile device
On Jun 22, 2012, at 6:22 PM, Andrea Pellegrini <andrea.pellegr...@gmail.com>
wrote:
> Hi all,
>
> I am doing some experiments w/ SMT and X86 in SE mode. I found something
> funny happening w/ the register file, that I wanted to clarify.
>
> Arch register 16 seems to be assigned always to the zeroRegister in the
> rename phase. In the renaming logic, reg 16 is always renamed to the same
> physical register (16 for thread0, 55 for thread1, 94 for thread2 and 133 for
> thread3). However, the logic in the rename and in the regfile does not match
> - and this creates some problems. In particular, in the regfile, the
> simulator does not seem to recognize that the register is a zeroReg (as
> determined instead from the rename stage). Is that a bug?
>
> Thanks,
>
> -Andrea
>
>
>
> ---------------------------
>
> rename_map.cc
>
> if (arch_reg < numLogicalIntRegs) {
>
> // Record the current physical register that is renamed to the
>
> // requested architected register.
>
> prev_reg = intRenameMap[arch_reg].physical_reg;
>
> // If it's not referencing the zero register, then rename the
>
> // register.
>
> if (arch_reg != intZeroReg) {
>
> renamed_reg = freeList->getIntReg();
>
> intRenameMap[arch_reg].physical_reg = renamed_reg;
>
> assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
>
> ---------------------------
>
> regfile.hh:
>
> ...
>
> if (reg_idx != TheISA::ZeroReg)
>
> intRegFile[reg_idx] = val;
>
> ...
>
> ---------------------------
>
> Looking at the definition of TheISA::ZeroReg I get:
>
> // semantically meaningful register indices
>
> //There is no such register in X86
>
> const int ZeroReg = NUM_INTREGS;
>
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