Hi,

I have a question about ARM mrc instructions in an exec trace. I am coming
across instructions that look like this:

172500: system.cpu + A0 T0 : @_start+36    :   mrc   r8, r95            :
IntAlu :  D=0x0000000080000000  FetchSeq=32  CPSeq=2

The mrc instruction reads from a cp15 coprocessor register, and from this
representation, I can't tell which. Also, from my understanding this
registers should have only one register field. The others should be CRn/CRm
and op codes for the coprocessor. It should look something like this:

MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}

The mcr instructions explicitly mention which register they are operating
on:

406040500: system.cpu + A0 T0 : @paging_init+1284    : mcr dccmvac (pipe
flush)   : No_OpClass :

Is the mrc trace output flawed? Or am I misunderstanding something?

Thanks,
Tony
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to