Hi Tony and Ali, I think I find another bug in generateDisassembly() for vmov. I came across this vmov instruction.
system.cpu0.fetch: [tid:0]: Instruction is: vmov.w f0, f5, f8 ... system.cpu0 T0 : 0x8978 : vmov.w f0, f5, f8 : SimdFloatMisc : D=0x0000000000000003 It shows f5 and f8 floating point registers are loaded to f0. However, vmov moves data from ARM core registers (R registers) to D registers. Since in Gem5 D registers are represented by F registers, I think the correct form should be "vmov.w f0, r5, r8". The assembly code generated by gcc shows "vmov d0, r5, r8". Thanks, Amin On Thu, Jul 19, 2012 at 10:41 AM, Anthony Gutierrez <[email protected]>wrote: > Ok, that's what I thought. I'll patch this up. > > Thanks, > Tony > > > On Thu, Jul 19, 2012 at 4:52 AM, Ali Saidi <[email protected]> wrote: > >> Hi Tony, >> >> It's a bug. generateDisassembly() needs to be overwritten for the mrc/mcr >> ops with code that produces the correct assembly. >> >> Thanks, >> Ali >> >> >> From: Anthony Gutierrez <[email protected]<mailto:[email protected]>> >> Reply-To: gem5 users mailing list <[email protected]<mailto: >> [email protected]>> >> Date: Wednesday, July 18, 2012 8:58 PM >> To: gem5 users mailing list <[email protected]<mailto: >> [email protected]>> >> Subject: [gem5-users] ARM mrc instruction in ExecAll trace. >> >> Hi, >> >> I have a question about ARM mrc instructions in an exec trace. I am >> coming across instructions that look like this: >> >> 172500: system.cpu + A0 T0 : @_start+36 : mrc r8, r95 : >> IntAlu : D=0x0000000080000000 FetchSeq=32 CPSeq=2 >> >> The mrc instruction reads from a cp15 coprocessor register, and from this >> representation, I can't tell which. Also, from my understanding this >> registers should have only one register field. The others should be CRn/CRm >> and op codes for the coprocessor. It should look something like this: >> >> MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} >> >> The mcr instructions explicitly mention which register they are operating >> on: >> >> 406040500: system.cpu + A0 T0 : @paging_init+1284 : mcr dccmvac (pipe >> flush) : No_OpClass : >> >> Is the mrc trace output flawed? Or am I misunderstanding something? >> >> Thanks, >> Tony >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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