You'll have to really dig into this code, and it depends on what you mean by all PC accesses. THe PC is accessed to computer PC relative branches and it's written when there is a branch commits. It can also get written when instructions are squashed due to memory ordering issues, or similar conflicts in the pipeline. The PC in the commit stage represents the committed state PC, the one in the fetch stage is completely speculative.
Ali On Sep 3, 2012, at 4:54 AM, AbhishekR wrote: > Hi all, > I am trying to track all the PC accesses in O3 CPU model. I see that there is > one PC maintained in fetch stage, and one in commit stage. I assume the fetch > stage PC represents the actual PC, can some please confirm this? > > I can see that commit stage's PC is forwarded to fetch stage when squashing > is required and fetch stage PC is updated accordingly. Are there any other > cases where fetch stage PC is updated based on commit stage PC? > > -- > Regards, > Abhishek Rhisheekesan > CIDSE, Arizona State University > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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