Hi Nilay,
Okay, if forcing the write back is not yet implemented. Then I want to
at least know the number of dirty lines in cache at the end of
simulation. How would I get this stat/parameter? Can you point me to
the right source file if I need to add this myself.
Many Thanks
Quoting Nilay Vaish <[email protected]>:
On Fri, 21 Sep 2012, [email protected] wrote:
Hi All,
How can I force writebacks of all the dirty cache lines after my
program have finished running in the simulator. What I mean is that
after the program finishes execution, the status of the last level
cache will have some dirty cache lines and I want to force those
cache lines to be written back to main memory and add this to the
trace of the program. Is there some kind of flush or trash
instruction to do this? or some command line option? Any help or
advice is much appreciated.
I think there are instructions in x86 ISA that flush one cache line
at a time. IIRC, x86 in gem5 does not support that instruction. You
can always implement such an instruction on your own using pseudo
ops. The main issue would be implementing the memory side behavior.
Ruby memory system supports flush requests (only works for the MOESI
hammer protocol). I am not aware if the classic memory system does
that. But it is possible to implement it.
--
Nilay
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