Hi Jagadish, I think you'll have to actually implement InOrder CPU checkpointing as I am not aware of anything being checked in that supports that features.
However, the checkpointing functions (serialize/unserialize and drain) in TimingSimple and O3 should give you a good idea of what you need to make this work. Thanks, Korey On Thu, Nov 1, 2012 at 4:59 PM, Nilay Vaish <[email protected]> wrote: > On Thu, 1 Nov 2012, Jagadish Kotra wrote: > > Hello Nilay, >> >> Yes, I could see Ruby being used while checkpointing. When I use the >> flags "--debug-flags=ProtocolTrace,**RubyGenerated" to confirm the same, >> I >> see the debug output containing the state transitions which look like: >> >> > Looking at the code for the in order cpu, it seems to me that you will > have to restore state directly to the inorder cpu, instead of first > restoring in to the timing cpu and then switching to the inorder cpu. > > If you still want to do this switch, I suggest you look into how the flag > deferRegistration is used for the o3 cpu. > > > -- > Nilay > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> > -- - Korey
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