Thank you very much for quick reply Fernando Endo.
.....
Musharaf
--- On Mon, 11/5/12, Fernando Endo <[email protected]> wrote:
From: Fernando Endo <[email protected]>
Subject: Re: [gem5-users] Need help to build custom. O3 in ARM
To: "gem5 users mailing list" <[email protected]>
Date: Monday, November 5, 2012, 12:11 AM
Hi,
Maybe this could help
you: http://www.hipeac.net/content/low-power-ecosystem-gem5-practical-user-experience
The first lecture was about how to implement a new O3 multicore.
Hope it will help you,
--Fernando A. Endo, PhD student and researcher
CEA Lab
and
Université de Grenoble, UJF
France
2012/11/5 Musharaf Hussain <[email protected]>
Hi Korey Sewell or All
I want to customize O3 CPU in ARM and I got a tutorial on gem5 website but that
is for SimpleAtomic CPU. I have to need to know how many modules or program or
file is related with O3 CPU. Korey Sewell , I have seen in max. program written
by you.
Please help me about that and to the point.
1. How many files is related with O3 to customize?
2. How rebuild it?
With best regards
----
Musharaf
--- On Fri, 11/2/12, Korey Sewell <[email protected]> wrote:
From: Korey Sewell <[email protected]>
Subject: Re: [gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS
To: "gem5 users mailing list"
<[email protected]>
Date: Friday, November 2, 2012, 7:52 AM
Hi Jagadish,
I think you'll have to actually implement InOrder CPU checkpointing as I am not
aware of anything being checked in that supports that features.
However, the checkpointing functions (serialize/unserialize and drain) in
TimingSimple and O3 should give you a good idea of what you need to make this
work.
Thanks,
Korey
On Thu, Nov 1, 2012 at 4:59 PM, Nilay Vaish <[email protected]> wrote:
On Thu, 1 Nov 2012, Jagadish Kotra wrote:
Hello Nilay,
Yes, I could see Ruby being used while checkpointing. When I use the
flags "--debug-flags=ProtocolTrace,RubyGenerated" to confirm the same, I
see the debug output containing the state transitions which look like:
Looking at the code for the in order cpu, it seems to me that you will have to
restore state directly to the inorder cpu, instead of first restoring in to the
timing cpu and then switching to the inorder cpu.
If you still want to do this switch, I suggest you look into how the flag
deferRegistration is used for the o3 cpu.
--
Nilay
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- Korey
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