The default only has a shared L2 cache. If you wanted to use private L2 caches per core you'd need to instantiate num_cores L2 caches and L2 busses, then connect them to the CPUs. E.g., you have to do something like this:
system.ls = [ L2Cache(clock = options.clock, size=...) for i in xrange(num_cores)] system.to_l2bus = [CoherentBus(clock=options.clock) for i in xrange(num_cores)] ... system.cpu[i].connectAllPorts(system.tol2bus[i], system.membus) If you want to have more exotic core-to-L2 mappings you'd need to change this slightly, but this should get you started. -Tony On Tue, Nov 6, 2012 at 6:14 PM, Mann <[email protected]> wrote: > Hi I am simulating with following script > "-n4 --timing --ruby --caches --cacheline_size=8 --l1d_assoc=2 > --l2_assoc=2 --l1d_size=32kB --l2_size=2MB" > Is my L2 is Private for processor or Shared? > > I am bit confused as going through CacheConfig.py > " > if options.l2cache: > system.cpu[i].connectAllPorts(system.tol2bus, system.membus) > else: > system.cpu[i].connectAllPorts(system.membus) > " > This is Defining new L2 for each processor or just connecting Poressor's > L1 to shared L2? > -- > Cheers........... > Mann > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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