You have to add --l2cache to enable the L2. Have a look at configs/common/Options.py
Check out the m5out/config.ini or the config.dot.pdf to see what system you are actually simulating. Andreas From: Abhishek Deshpande <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Friday, 23 November 2012 13:00 To: "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Query on Cache Profiling Hello, I am naive user of gem5. I am trying to find Write Latencies to L1, L2 and LLC caches. I need Read/Write Hits/Misses on L1, L2, LLC with respect to ticks. I have executed command line: ./build/ALPHA/gem5.opt --quiet --outdir=result --trace-file=trace.out --debug-flags=Cache configs/example/se.py --clock=1.0GHz --cpu-type=detailed --caches --l1d_size=32kB --l1i_size=32kB --l2_size=256kB --l3_size=8192kB -c v1-splash-alpha/splash2/codes/kernels/fft/FFT I am not able to find L2, LLC data in trace.out. Please help me in suggesting any flags that will give me such output. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
