Hello everyone,
I use ruby (MOESI_CMP_directory) and I want to simulate a system
with one CPU (frequency=2GHz) and L1 and L2 caches (frequency=4GHz).
I also want the bus between cpu and cache
to run at 4GHz with width 32 bits. So I have to set the cpu
frequency equal to 4GHz (ruby_fs.py -> CPUClass.clock = '2GHz')
and ruby frequency equal to 2GHz
(Ruby.py -> system.ruby = RubySystem(clock = 4,
stats_filename = options.ruby_stats,
no_mem_vec = options.use_map)).
I suppose these changes are right, my main concern is:
Do I have to change system.piobus frequency
to 4GHz and width to 4 bytes (file FSConfig.py, function
makeLinuxAlphaRubySystem)?
Is this the bus between cpu and L1 cache? If it is not
how can I configure the bus between L1 and CPU?
I am little bit confused about the interconnection system.
Thanks in advance for any help,
Pavlos
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