On Sat, 24 Nov 2012, Frank Yang wrote:
Hi All,
I am trying to dig into Gem5 but I found it's fairly complicated. Can
someone give me any hint on how gem5 bring the concept of timing into
those CPU models? I can understand that each instruction is divided into
several stages, but how is the magic gem5 does to fetch the instruction
in each cycle? And how to pass those intermediate value of each
instruction generated to the next cycle? I am still in the world of
Verilog/VHDL, so it's hard for me to figure this out in C++. Thanks for
any of your input.
Some documentation on out-of-order cpu is available on gem5.org.
--
Nilay
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