The idea isn't much different from an RTL simulation. In an RTL sim,
time is advanced by a step, all the flops are updated to their new
values, time is advanced by another step, etc. gem5 does the same thing
with processor structures--for every time step, structures get updated.
There are two key differences: 1.) gem5 implements a behavioral model
for each structure in C++ rather than try to figure out what the
structure would actually look like if made out of gates. 2.) Not every
structure is updated in every time step; instead, when a structure is
updated, it can schedule an event for a later time that will trigger its
next update.
You could try running a simulation for 5-10 instructions with something
like the O3CPUAll debug flag. It's really helpful to see instructions
actually passing through the CPU. http://gem5.org/Debugging
-Erik
On 24/11/12 09:32, Frank Yang wrote:
Hi All,
I am trying to dig into Gem5 but I found it's fairly complicated. Can someone
give me any hint on how gem5 bring the concept of timing into those CPU models?
I can understand that each instruction is divided into several stages, but how
is the magic gem5 does to fetch the instruction in each cycle? And how to pass
those intermediate value of each instruction generated to the next cycle? I am
still in the world of Verilog/VHDL, so it's hard for me to figure this out in
C++. Thanks for any of your input.
-Yang
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