I think the Ruby port might not send an addr range change on init as it assumes it is connected to a CPU that does not care. The bus, however, does.
Andreas On 24/11/2012 13:52, "Pavlos Maniotis" <[email protected]> wrote: >Hello everyone, > >In ruby_fs.py I try to connect cpu ports and ruby ports through >a coherent bus. I changed these two lines that connect the ports >directly: > > cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave > cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave > >to this: > > cpu.tol1bus = CoherentBus() > cpu.tol1bus.clock = '2GHz' > cpu.tol1bus.width = 8 > cpu.icache_port = cpu.tol1bus.slave > cpu.dcache_port = cpu.tol1bus.slave > system.ruby._cpu_ruby_ports[i].slave = cpu.tol1bus.master > >but when I try to run a simulation I get this message: > >**** REAL SIMULATION **** >info: Entering event queue @ 0. Starting simulation... >gem5.opt: build/ALPHA/mem/bus.cc:343: PortID BaseBus::findPort(Addr): >Assertion `gotAllAddrRanges' failed. > > >Does anyone have an idea what is going wrong? > >Thanks in advance, >Pavlos > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
