I would think adding this to RubyPort::init() should do the trick:
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
(*p)->sendRangeChange();
}
If it works submit a patch to the review board.
Andreas
On 24/11/2012 16:56, "Pavlos Maniotis" <[email protected]> wrote:
>What do you think should I do to solve this problem? I use gem5
>for about 1-2 months and there are many things that I cannot
>understand yet! It's chaotic to me.
>
>Pavlos
>
>On Sat, 2012-11-24 at 15:33 +0000, Andreas Hansson wrote:
>> I think the Ruby port might not send an addr range change on init as it
>> assumes it is connected to a CPU that does not care. The bus, however,
>> does.
>>
>> Andreas
>>
>> On 24/11/2012 13:52, "Pavlos Maniotis" <[email protected]> wrote:
>>
>> >Hello everyone,
>> >
>> >In ruby_fs.py I try to connect cpu ports and ruby ports through
>> >a coherent bus. I changed these two lines that connect the ports
>> >directly:
>> >
>> > cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
>> > cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
>> >
>> >to this:
>> >
>> > cpu.tol1bus = CoherentBus()
>> > cpu.tol1bus.clock = '2GHz'
>> > cpu.tol1bus.width = 8
>> > cpu.icache_port = cpu.tol1bus.slave
>> > cpu.dcache_port = cpu.tol1bus.slave
>> > system.ruby._cpu_ruby_ports[i].slave = cpu.tol1bus.master
>> >
>> >but when I try to run a simulation I get this message:
>> >
>> >**** REAL SIMULATION ****
>> >info: Entering event queue @ 0. Starting simulation...
>> >gem5.opt: build/ALPHA/mem/bus.cc:343: PortID BaseBus::findPort(Addr):
>> >Assertion `gotAllAddrRanges' failed.
>> >
>> >
>> >Does anyone have an idea what is going wrong?
>> >
>> >Thanks in advance,
>> >Pavlos
>> >
>> >_______________________________________________
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>> >
>>
>>
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