Hello All,
I have successfully modified the gem5 Ruby Cache Memory model suit my needs. At
run-time, the benchmark I run terminates due to a invalid state transition. I
have a trace of the transitions that I have got through the debug flag
"ProtocolTrace". Can somebody give me a clue on how I should interpret the
trace printed out and How I should go about debugging. Any help appreciated.
16209000 0 Seq Begin > [0x154890,
line 0x154880] ST
16209500 0 Seq Done > [0x152490,
line 0x152480] 109 cycles
16209500 0 L1Cache Data_all_Acks IM>M [0x152480,
line 0x152480]
16210000 0 L2Cache L1_GETX NP>IM [0x154080,
line 0x154080]
16210500 0 L2Cache L1_PUTX MT>M [0x134480,
line 0x134480]
16210500 0 L1Cache L1_Replacement M>M_I [0x134880,
line 0x134880]
16210500 0 L1Cache Store NP>IM [0x154880,
line 0x154880]
16211000 0 L2Cache Mem_Data IM>MT_MB [0x152080,
line 0x152080]
16211000 0 Seq Begin > [0x4e6c0, line
0x4e6c0] LD
16212500 0 Seq Done > [0x4e6c0, line
0x4e6c0] 3 cycles
16212500 0 L1Cache Load M>M [0x4e6c0, line
0x4e6c0]
16213000 0 L2Cache Exclusive_Unblock MT_MB>MT [0x152480,
line 0x152480]
16214000 0 L1Cache WB_Ack M_I>I [0x134480,
line 0x134480]
16214000 0 Directory Fetch I>IM [0x154080,
line 0x154080]
16214500 0 Seq Done > [0x152090,
line 0x152080] 129 cycles
16214500 0 L1Cache Data_all_Acks IM>M [0x152080,
line 0x152080]
16215000 0 L2Cache L1_GETX NP>IM [0x154480,
line 0x154480]
16215000 0 Directory Memory_Data IM>M [0x152880,
line 0x152880]
16215000 0 Seq Begin > [0x154c90,
line 0x154c80] ST
16215000 0 Seq Begin > [0x4e6c0, line
0x4e6c0] LD
16215500 0 L2Cache L1_PUTX MT>M [0x134880,
line 0x134880]
16216500 0 L1Cache L1_Replacement M>M_I [0x134c80,
line 0x134c80]
16216500 0 L1Cache Store NP>IM [0x154c80,
line 0x154c80]
16216500 0 Seq Done > [0x4e6c0, line
0x4e6c0] 3 cycles
16216500 0 L1Cache Load M>M [0x4e6c0, line
0x4e6c0]
16217500 0 L2Cache L1_GETX NP>IM [0x154880,
line 0x154880]
16218000 0 L2Cache Exclusive_Unblock MT_MB>MT [0x152080,
line 0x152080]
16218500 0 L2Cache Mem_Data IM>MT_MB [0x152880,
line 0x152880]
16219000 0 L1Cache WB_Ack M_I>I [0x134880,
line 0x134880]
16219000 0 Directory Fetch I>IM [0x154480,
line 0x154480]
16219000 0 Seq Begin > [0x155090,
line 0x155080] ST
16220000 0 Directory Memory_Data IM>M [0x152c80,
line 0x152c80]
16220500 0 L2Cache L1_PUTX MT>M [0x134c80,
line 0x134c80]
16220500 0 L1Cache L1_Replacement M>M_I [0x135080,
line 0x135080]
16220500 0 L1Cache Store NP>IM [0x155080,
line 0x155080]
16221500 0 Directory Fetch I>IM [0x154880,
line 0x154880]
16222000 0 Seq Done > [0x152890,
line 0x152880] 126 cycles
16222000 0 L1Cache Data_all_Acks IM>M [0x152880,
line 0x152880]
16222000 0 Seq Begin > [0x4e6c0, line
0x4e6c0] LD
16223000 0 L2Cache L1_GETX NP>IM [0x154c80,
line 0x154c80]
16223500 0 L2Cache Mem_Data IM>MT_MB [0x152c80,
line 0x152c80]
16223500 0 Seq Done > [0x4e6c0, line
0x4e6c0] 3 cycles
16223500 0 L1Cache Load M>M [0x4e6c0, line
0x4e6c0]
16224000 0 L1Cache WB_Ack M_I>I [0x134c80,
line 0x134c80]
16225500 0 L2Cache Exclusive_Unblock MT_MB>MT [0x152880,
line 0x152880]
16226000 0 L2Cache L1_PUTX MT>M [0x135080,
line 0x135080]
16226000 0 Seq Begin > [0x155490,
line 0x155480] ST
16227000 0 Seq Done > [0x152c90,
line 0x152c80] 124 cycles
16227000 0 L1Cache Data_all_Acks IM>M [0x152c80,
line 0x152c80]
16227000 0 Seq Begin > [0x4e6c0, line
0x4e6c0] LD
16227500 0 L1Cache L1_Replacement M>M_I [0x135480,
line 0x135480]
16227500 0 L1Cache Store NP>IM [0x155480,
line 0x155480]
16227500 0 Directory Memory_Data IM>M [0x153080,
line 0x153080]
16228000 0 L2Cache L1_GETX NP>IM [0x155080,
line 0x155080]
16228500 0 L1Cache Load NP>IS [0x4e6c0, line
0x4e6c0]
16229000 0 Directory Fetch I>IM [0x154c80,
line 0x154c80]
16229500 0 L1Cache WB_Ack M_I>I [0x135080,
line 0x135080]
16230500 0 L2Cache Exclusive_Unblock MT_MB>MT [0x152c80,
line 0x152c80]
16231000 0 L2Cache Mem_Data IM>MT_MB [0x153080,
line 0x153080]
16232000 0 Directory Fetch I>IM [0x155080,
line 0x155080]
16232500 0 Directory Memory_Data IM>M [0x153480,
line 0x153480]
16233000 0 L2Cache L1_PUTX MT>M [0x135480,
line 0x135480]
16234500 0 Seq Done > [0x153090,
line 0x153080] 131 cycles
16234500 0 L1Cache Data_all_Acks IM>M [0x153080,
line 0x153080]
16235500 0 L2Cache L1_GETX NP>IM [0x155480,
line 0x155480]
16235500 0 L2Cache L1_GETS MT>MT_IIB [0x4e6c0, line
0x4e6c0]
16236000 0 L2Cache Mem_Data IM>MT_MB [0x153480,
line 0x153480]
16236500 0 L1Cache WB_Ack M_I>I [0x135480,
line 0x135480]
16238000 0 L2Cache Exclusive_Unblock MT_MB>MT [0x153080,
line 0x153080]
fatal: Invalid transition
system.l1_cntrl0 time: 32478 addr: [0x4e6c0, line 0x4e6c0] event: Fwd_GETS
state: IS
@ cycle 16239000
[doTransitionWorker:build/ALPHA_MESI_CMP_directory/mem/protocol/L1Cache_Transitions.cc,
line 371]
Memory Usage: 4412416 KBytes
Regards,
Udayan
Electrical and Computer Engineering
Purdue University
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