On Thu, 13 Dec 2012, Yongbing Huang wrote:
Hi all,I set the associative of L2 cache to 16 in the configuration file when booting ARM FS simulator. However, the boot log of gem5 shown below indicates that the l2 cache is 8-way. I wonder whether the boot information is not correct or the specified configuration is actually ignored. [ 0.014981] L2x0 series cache controller enabled [ 0.014987] l2x0: 8 ways, CACHE_ID 0xffffffff, AUX_CTRL 0xc2520fff"
If you figure out how the operating system learns about the associativity of the cache, I think you will be able to nail which of the hypothesis you suggested is correct.
-- Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
