Hi Abu If you google 'mcr icimvau', you will find answer by yourself. Here is a good answer. http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/CASES_2012_Lazy.pdf
In the paper above, it says it is a *ARM system control instruction* which invalidates a single cache line if I understand correctly from the literal lines. 2013/2/23 Abu Saad <[email protected]> > Hi all > I want to know where(which program contains in gem5) used mcr icimvauand mcr > icialluis instruction? > Anyone could help please! > > with best regards > --- > Abusaad > > > On Sat, Feb 23, 2013 at 3:51 AM, Abu Saad <[email protected]> wrote: > >> Hi all >> I want to know where used mcr icimvau and mcr icialluis instruction? >> Anyone could help please! >> >> with best regards >> --- >> Abusaad >> >> > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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