Hi Negar, Seen from the CPU, memory latency is a function of many things (caches, interconnect, DRAM), and it is not "calculated", but rather a result of these blocks and their interactions. If you look at the statistics of the caches for example you can get an idea of their miss latencies (for both L1 and L2). If you are only interested in the latency associated with the DRAM controller, then the statistics of the SimpleDRAM module will give you an idea (see e.g. totMemAccLat).
I hope that helps. Andreas On 27/02/2013 13:39, "Negar Miralaei" <[email protected]> wrote: >Hi all, > >Could anyone please guide me, in which functions or files related to the >physical memory (in the gem5 source code) we have cycle calculation or >cycle counter? And, whether the ticksToCycles() is used to calculate the >cpu cycles after receiving the number of ticks from memory or just a >counter like cycle++? In other words, how and where (in code) does gem5 >calculate the number of cycles that has spent in physical memory? > >Thanks >Negar >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
