Hi Negar, I don't quite follow what the issue is, but keep in mind that the memory timings are not altered when you adjust the CPU frequency (and neither are the bus, I/O device latencies etc).
Andreas On 27/02/2013 14:27, "Negar Miralaei" <[email protected]> wrote: >Hi Andreas, > >Thank you very much for your quick response. It's exactly what I need :) > >Actually, I'm trying to find out why for some special frequencies >(clocks), for the same application (by changing the latency as well as >the frequency, so everything is under same conditions except the freq), >the number of cycles are far more than what they should be (compare to >other frequencies) which results in wrong number of sim-ticks too! Then, >I did some debugging and now I know one of the main problems happens in >physical memory when a miss occurs. I'm looking into the SimpleDRAM code >to find it hopefully. > >Thanks >Negar > > > >On 27/02/13 14:05, Andreas Hansson wrote: >> Hi Negar, >> >> Seen from the CPU, memory latency is a function of many things (caches, >> interconnect, DRAM), and it is not "calculated", but rather a result of >> these blocks and their interactions. If you look at the statistics of >>the >> caches for example you can get an idea of their miss latencies (for both >> L1 and L2). If you are only interested in the latency associated with >>the >> DRAM controller, then the statistics of the SimpleDRAM module will give >> you an idea (see e.g. totMemAccLat). >> >> I hope that helps. >> >> Andreas >> >> >> On 27/02/2013 13:39, "Negar Miralaei" <[email protected]> wrote: >> >>> Hi all, >>> >>> Could anyone please guide me, in which functions or files related to >>>the >>> physical memory (in the gem5 source code) we have cycle calculation or >>> cycle counter? And, whether the ticksToCycles() is used to calculate >>>the >>> cpu cycles after receiving the number of ticks from memory or just a >>> counter like cycle++? In other words, how and where (in code) does gem5 >>> calculate the number of cycles that has spent in physical memory? >>> >>> Thanks >>> Negar >>> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >>confidential and may also be privileged. If you are not the intended >>recipient, please notify the sender immediately and do not disclose the >>contents to any other person, use it for any purpose, or store or copy >>the information in any medium. Thank you. >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
