The simple cpus models access the cache for every instruction, while the o3 model accesses the cache a line at a time and keeps that line in a buffer. If you're in a tight loop that stays in that buffer it won't fetch.
Ali On Mar 5, 2013, at 5:23 AM, Maxime Chéramy <[email protected]> wrote: > Hello, > > I am using gem5 for x86 with Ruby (MESI protocol) in SE mode. According to > the number of accesses to the L1 instruction cache, the number of > instructions running the simulation with --cpu-type=timing is ~6500000 while > using --cpu-type=detailed, it's only ~1700000. > I also ran the same program using cachegrind and I have ~4500000 instruction > references. > > Could someone help me to understand what causes such a difference between the > cpu models and the results given by cachegrind? > > Thank you. > > Best regards, > > Maxime. > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
