Ali Saidi <saidi <at> umich.edu> writes: > > Hi Amit, > > It seems like you managed to find a case in the o3 cpu that isn't being handled correctly. It looks like a load > that is uncacheable isn't being executed at the right time and that is what caused the panic. You'll need to > use the sequence number of the instruction and trace trough the pipeline what is happening and why the > commit stage thought the instruction was complete when it isn't. > > Thanks, > Ali > > On Oct 17, 2012, at 1:29 AM, Amit Singh wrote: > > > > > Hey.... > > > > Is this some generic problem with gem5 or I am doing something wrong....?? > > Simulation is doing good for default input parameters but when I am specifying parameters then following > error is coming again and again. > > > > command line: build/ARM/gem5.opt --outdir=bbench2 configs/example/fs.py -b bbench-gb > --num-cpus=2 --caches --l1d_size=32kB --l1d_assoc=4 --l1i_size=32kB -- l1i_assoc=4 --l2cache > --l2_size=512kB --l2_assoc=8 --cacheline_size=64 -- kernel=vmlinux.smp.mouse.arm > --frame-capture --cpu-type=arm_detailed > > Global frequency set at 1000000000000 ticks per second > > info: kernel located at: /home/amit/Gem5+/dist/arm-system-2011- 08/binaries/vmlinux.smp.mouse.arm > > Listening for system connection on port 5900 > > Listening for system connection on port 3456 > > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > > 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 > > info: Using bootloader at address 0x80000000 > > **** REAL SIMULATION **** > > info: Entering event queue @ 0. Starting simulation... > > warn: The clidr register always reports 0 caches. > > warn: clidr LoUIS field of 0b001 to match current ARM implementations. > > warn: The csselr register isn't implemented. > > warn: instruction 'mcr bpiallis' unimplemented > > warn: instruction 'mcr icialluis' unimplemented > > 4036799500: system.terminal: attach terminal 0 > > warn: The ccsidr register isn't implemented and always reads as 0. > > warn: instruction 'mcr dccimvac' unimplemented > > warn: instruction 'mcr dccmvau' unimplemented > > warn: instruction 'mcr icimvau' unimplemented > > warn: instruction 'mcr bpiallis' unimplemented > > warn: allocating bonus target for snoop > > warn: allocating bonus target for snoop > > warn: LCD dual screen mode not supported > > warn: instruction 'mcr bpiallis' unimplemented > > warn: instruction 'mcr icialluis' unimplemented > > warn: instruction 'mcr bpiallis' unimplemented > > panic: Uncachable load [sn:42fa3c1] PC (0xc016e0cc=>0xc016e0d0).(0=>1) > > @ cycle 850974449500 > > [invoke:build/ARM/arch/generic/debugfaults.hh, line 94] > > Memory Usage: 606896 KBytes > > Program aborted at cycle 850974449500 > > Aborted (core dumped) > > > > > > plaease tell what is the reason and how to fix it..? > > > > Thanx in advance... > > _______________________________________________ > > gem5-users mailing list > > gem5-users <at> gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
I'm experiencing a similar problem using a clean copy of gem5-dev. Did anyone find a fix? command line: ../gem5/build/ARM/gem5.fast --outdir=./simple ../gem5/configs/example/fs.py --cpu-type=ar m_detailed --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=2MB -b simple --kernel=vmlinux- 3.3-arm-vexpress-emm-pcie --machine-type=VExpress_EMM -n 4 Global frequency set at 1000000000000 ticks per second info: kernel located at: ../gem5/system/arm/binaries/vmlinux-3.3-arm-vexpress- emm-pcie Listening for system connection on port 5900 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7001 0: system.remote_gdb.listener: listening for remote gdb on port 7002 0: system.remote_gdb.listener: listening for remote gdb on port 7003 info: Using bootloader at address 0x10 **** REAL SIMULATION **** info: Entering event queue @ 0. Starting simulation... warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented panic: Uncachable load [sn:adaa] PC (0x80017e54=>0x80017e58).(0=>1) @ cycle 70634247500 [invoke:build/ARM/arch/generic/debugfaults.hh, line 94] Memory Usage: 2404444 KBytes Program aborted at cycle 70634247500 Thanks, Tom _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
