Hi gem5 team,
My research is to design and simulate a multicore architecture under mesh
topology with each core having its own memory, which cannot be seen by other
processing units. Communication is done by interconnection of L1 caches of
different cores.
I find that the memory model is based on one single instance of physical memory
at bottom. Although distributed generalized memories are enabled in this way
http://reviews.gem5.org/r/1113/diff/?page=3, it seems that no one has done
private memory stuff.
Thus here comes the question, is it reasonable and feasible to adapt the source
code of the interface between NoC and memory to my target architecture?
I am a newbie in gem5 and hope it won't bother you. I would appreciate that if
anyone kindly gives me a hint.
Regards,
-Xiaobin
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