Hi Andreas, Thank you for your prompt reply and these days I am chewing on it. Your advices are very helpful and I am currently look into corresponding source code. In the URL:http://reviews.gem5.org/r/1113/diff/?page=3, you did a lot of work and added distributed memory to gem5. Is the updated version of gem5 able to run software? Since the memory is distributed, how can I set the latencies and bandwidth for different pieces of memories? (Since closer memory provides lower latency)
Thank you in advance for your reading this and reply. -Xiaobin On Apr 3, 2013, at 9:36 AM, Andreas Hansson <[email protected]> wrote: > Hi Xiaobin, > > The short answer: Not out of the box. > > The long answer: > > You can definitely create the kind of system that you are describing in gem5, > with a "non-global" address map, but do not expect to easily run an OS on top > of it. The patch you describe lets you have multiple different memories, and > there is nothing forcing you to give all the CPUs the same memory map. > However, if you intend to actually run software, gem5 currently assumes you > run a single OS instance, and changing that would probably be quite a task. > > The one "hack" I can think of would be to treat each core+$es as a machine, > and then instead of connecting them with ethernet, connect them with a > non-coherent bus. Perhaps something like this could do what you want it to do. > > Andreas > > From: Xiaobin Liu <[email protected]> > Reply-To: gem5 users mailing list <[email protected]> > Date: Tuesday, 2 April 2013 15:34 > To: "[email protected]" <[email protected]> > Subject: [gem5-users] Each Core with private memory > > Hi gem5 team, > > My research is to design and simulate a multicore architecture under mesh > topology with each core having its own memory, which cannot be seen by other > processing units. Communication is done by interconnection of L1 caches of > different cores. > I find that the memory model is based on one single instance of physical > memory at bottom. Although distributed generalized memories are enabled in > this way http://reviews.gem5.org/r/1113/diff/?page=3, it seems that no one > has done private memory stuff. > Thus here comes the question, is it reasonable and feasible to adapt the > source code of the interface between NoC and memory to my target > architecture? > I am a newbie in gem5 and hope it won't bother you. I would appreciate that > if anyone kindly gives me a hint. > > Regards, > -Xiaobin > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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