Hi,
I am running x86 ISA in SE mode.
I want to read source registers of instructions in commit stage. When I try
to learn the number of their source regs, there are some weird numbers. My
exact usage is, in src/cpu/o3/commit_impl.hh :
if (commit_succes) {
int opC = head_inst -> staticInst -> opClass(); // I need only
intAlu , intMult and intDiv instructions
int srcRegs = head_inst->staticInst->numSrcRegs(); // Then I write
these numbers to a text file.
I simulated hello world program for testing. When I checked the text file,
there were some unrealistic numbers. For example; there were "and"
instructions with 3 and 4 source regs, "xor" instruction with 3 source
regs, "wrip" instruction (write instruction pointer) with 8 (!!!) source
regs. Then I checked implementation of "and" instruction in
build/X86/arch/x86/generated/decoder.cc . There are 4 AND instructions with
"and" mnemonic. All of them work with 2 source regs. However, "And" and
"AndFlags" have different implementations. They look like this :
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numIntDestRegs = 0;
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(src1, foldOBit);
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(src2, foldOBit);
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(dest, foldOBit); // Why this line
is needed?
_destRegIdx[_numDestRegs++] = INTREG_FOLDED(dest, foldOBit);
_numIntDestRegs++;
Many instructions were implemented in that way like Sub,Add etc. Is there a
problem or were they needed to implement in that way?
I am also getting assertion fail when I use readArchIntReg() methods in
cpu.cc . My usage is, in src/cpu/o3/commit_impl.hh :
head_inst->cpu->readArchIntReg((head_inst->staticInst->srcRegIdx(0)),head_inst->threadNumber);
It says that srcRegIdx() returns architectural reg no, but I get assertion
error. What am I missing or should I use instead of this method?
Best regards.
Serdar Zafer CAN
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