Hi,
First of all, a little disclaimer : I am not absolutely sure that my
explanations are correct since it has been a long time I updated my
version. However, last time I checked, that is how I understood it.
But first, do you have a particular example of a XOR or a AND with more
than 2 source registers, did you follow it in a trace
(--debug-flags=All) to see what is happening?
Regarding the wrip, it is my understanding that it has 8 sources because
flags are not considered as being a single register, so several flags
equals several registers equals several dependencies (I may be wrong on
that though). However it *does* have 8 if you check a trace.
Concerning your code example, I suppose that the line with a comment at
the end is needed in case you have to merge the destination register
with the result of the operation e.g. if you "and" ebx with ecx into
eax, you still need the 32 upper bits of rax to merge with the result of
your 32-bit and).
Last, maybe you should give us the assertion error and in which context
it fails (what instruction, what register, etc). Nonetheless, to read
the value of the source registers at commit, maybe you could try to put
something like that in dyn_inst.hh (to call at commit) :
std::deque<IntReg> * getPredRegs() {
std::deque<IntReg> *result = new std::deque<IntReg>();
for(unsigned i = 0; i < this->numSrcRegs(); i++) {
if(this->renamedSrcRegIdx(i) >=
this->cpu->scoreboard.numPhysicalIntRegs) {
union {
FloatReg float_pred;
IntReg int_pred;
} tmp;
tmp.float_pred =
this->cpu->readFloatReg(this->renamedSrcRegIdx(i));
result->push_back(tmp.int_pred);
} else {
result->push_back(this->cpu->readIntReg(this->renamedSrcRegIdx(i)));
}
}
return result;
}
This returns a deque containing the values of the source registers. You
will potentially need to change private/protected stuff to public but it
does the trick for me. Hope it helps.
Le 23/04/2013 12:54, Serdar Zafer Can a écrit :
Hi,
I am running x86 ISA in SE mode.
I want to read source registers of instructions in commit stage. When
I try to learn the number of their source regs, there are some weird
numbers. My exact usage is, in src/cpu/o3/commit_impl.hh :
if (commit_succes) {
int opC = head_inst -> staticInst -> opClass(); // I need only
intAlu , intMult and intDiv instructions
int srcRegs = head_inst->staticInst->numSrcRegs(); // Then I
write these numbers to a text file.
I simulated hello world program for testing. When I checked the text
file, there were some unrealistic numbers. For example; there were
"and" instructions with 3 and 4 source regs, "xor" instruction with 3
source regs, "wrip" instruction (write instruction pointer) with 8
(!!!) source regs. Then I checked implementation of "and" instruction
in build/X86/arch/x86/generated/decoder.cc . There are 4 AND
instructions with "and" mnemonic. All of them work with 2 source regs.
However, "And" and "AndFlags" have different implementations. They
look like this :
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numIntDestRegs = 0;
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(src1, foldOBit);
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(src2, foldOBit);
_srcRegIdx[_numSrcRegs++] = INTREG_FOLDED(dest, foldOBit); // Why this
line is needed?
_destRegIdx[_numDestRegs++] = INTREG_FOLDED(dest, foldOBit);
_numIntDestRegs++;
Many instructions were implemented in that way like Sub,Add etc. Is
there a problem or were they needed to implement in that way?
I am also getting assertion fail when I use readArchIntReg() methods
in cpu.cc . My usage is, in src/cpu/o3/commit_impl.hh :
head_inst->cpu->readArchIntReg((head_inst->staticInst->srcRegIdx(0)),head_inst->threadNumber);
It says that srcRegIdx() returns architectural reg no, but I get
assertion error. What am I missing or should I use instead of this method?
Best regards.
Serdar Zafer CAN
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