Dear all, I'm using gem5 to simulating a cache optimization, but met some trouble. Help me out, when you found my mistakes. Thanks! It is configured as alpha inorder CPU with the build_opt given as "ALPHA_MESI_CMP_directory", and the CPU and caches are set as follows:
options.cpu_type = 'inorder' options.caches = 'caches' options.l1d_size = '64kB' options.l1i_size = '64kB' options.l2cache = 'True' options.l2_size = '1MB' options.l3cache = 'True' options.l3_size = '8MB' My problem is that when I look at the stats result for benchmark SPEC cpu 2006 bzip2, I found the reduction of overall dcache miss latency(15619739000 ticks) is much larger than that of sim ticks (5569683000 ticks). How could it be? If the CPU is inorder and the IPC is lease than 1, the variance of L1 miss latency should roughly smaller than that of CPU time. Note that optimizations I made did not influence the miss latency statistics. So what's the explanation? And how can I get the "CPU time contribution Ratio of cache hierarchy" from the simulator? Anybody's response is welcome! -- Chao Zhang School of EECS, Peking University
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