Hi, I'm struggling to find how to control the latency to DDR controller seen by the CPU (and the CPU only) in ARM FS.
I tried controlling the l2 response_latency (which BaseCache.py descibes as "Additional cache latency for the return path to core on a miss") , but this also seems to impact the latency seen by initiators coming through the IOCache E.g. testsys.iocache.ReadReq_avg_miss_latency::realview.ethernet increases as I increase response_latency in the L2 cache. Is there another mechanism I am missing which would allow me to control the CPU to DDR controller latency? Thanks for your advise, Stuart.
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