Hi Bonzi,
Could you post it as a patch perhaps? I'd be very keen to see what you've done.
Have you evaluated the performance implication and the behavioural differences
between the two?
Thanks,
Andreas
From: Hao Wang <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Thursday, 9 May 2013 23:35
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] SimpleDRAM accuracy
Hi Amin,
I have a cycle-driven version of the memory controller that models the various
DRAM timing parameters and per-bank states.
I may copy to you if you want.
Bonzi
On Wed, May 8, 2013 at 8:20 PM, Amin Farmahini
<[email protected]<mailto:[email protected]>> wrote:
Hi,
Comparing SimpleDRAM model and DRAMSim2 model, I was wondering how timing
accurate SimpleDRAM is for memory-intensive applications? This might be a
question for Andreas and Tao and I know this is a very general question, but
any thoughts on this would be appreciated. Andreas mentioned that SimpleDRAM
provides "good-enough accuracy." More information on the accuracy would be
great.
I realized some detailed parameters such as FAW are integrated into SimpleDRAM,
and some other like RRD are left out. So my next question is whether there are
any plans to model more detailed DRAM behavior?
Thanks,
Amin
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------------------------------------------------------
Wang, Hao
http://homepages.cae.wisc.edu/~wangh/
Ph.D. candidate
Dept. of Electrical & Computer Engineering
University of Wisconsin, Madison
B.S. from
Department of Microelectronics
School of Electronics Engineering and Computer Science
Peking University
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