Hi, Amin, Thanks for confirm.
I read the source code in src/cpu/o3, and in the rename_impl.hh, there are 2 functions. "DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)" "DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)", I beleieve that these 2 functions give the register new name. So I guess the "bypassing the rename" means (1)we make the new name = old name, so it will disable the renaming. (2)make the rename width to unlimited, so there is no block in this stage.(3) make the delay to timing buffer to 0, so it will forward to next stage(iew) without any ticking. I maybe totally wrong, please correct me. Thanks in advance. Regards On Fri, Jun 7, 2013 at 11:08 PM, Amin Farmahini <amin...@gmail.com> wrote: > Yes, as far as I know it does not work. > O3 to InOrder hack is the way to go. > > Thanks, > Amin > > > On Fri, Jun 7, 2013 at 4:56 PM, Xiangyang Guo <ece...@gmail.com> wrote: > >> Hi, gem5-users, >> >> I want to use the InOrder CPU for ARM ISA, but it is not implemented. in >> the post, >> http://thread.gmane.org/gmane.comp.emulators.m5.users/10970/focus=12145, >> there are three patches, I tried, but it doesn't work and the third patch >> doesn't finish I think. >> >> Ashish told me that we can converted O3 to inorder (bypassing register >> renaming and using inorder issue and commit). So does this work? Could any >> experienced developer tell me if I can follow this way? Thanks in advance >> >> Regards >> >> Xiangyang >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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