Hi Zhiguo, I marked this email for response so I will get back to it definitely. However, that will not be until after next Monday unfortunately.
I may have some patches done in open-source I can pass you but in all likelihood I can give you advice/direction. -Korey On Wed, Aug 28, 2013 at 12:50 AM, GE ZHIGUO <ge.zhi...@huawei.com> wrote: > Hi, Korey > > > > Whether are you going to submit the patch recently? > > I am going to enable ARM/InOrder CPU model. > > > Can you please provide help and guidances when I do the enabling? > > Thanks and best regards, > Zhiguo > > ------------------------------ > *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on > behalf of Korey Sewell [ksew...@umich.edu] > *Sent:* Saturday, June 08, 2013 10:58 PM > *To:* gem5 users mailing list > *Subject:* Re: [gem5-users] ARM InOrder implement > > In my opinion, > there are 3 ways to go (in order of speed of functionality): > 1. configure o3 ARM to be inorder ARM > ===> If you make all the buffer sizes 1, you have a single-issue in-order > machine > 2. pick up the patches on reviewboard, use gem5-dev for questions as you > bring them up > ===> I'd help answer questions there, but that's going to mean you have to > learn some internals of the InOrder model > 3. Wait a few months for the ARM InOrder patch from myself or others. > ===> There is some legal clearing I have to do (I'm not a full-time > student anymore!). However, it's my goal to post relevant patches into the > tree. I anticipate that done at least by the next gem5 workshop but please > don't "quote" me on that! > > > > On Sat, Jun 8, 2013 at 5:16 AM, Xiangyang Guo <ece...@gmail.com> wrote: > >> Hi, Amin, >> >> Thanks for confirm. >> >> I read the source code in src/cpu/o3, and in the rename_impl.hh, there >> are 2 functions. >> >> "DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)" >> >> "DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)", >> >> I beleieve that these 2 functions give the register new name. So I guess >> the "bypassing the rename" means (1)we make the new name = old name, so it >> will disable the renaming. (2)make the rename width to unlimited, so there >> is no block in this stage.(3) make the delay to timing buffer to 0, so it >> will forward to next stage(iew) without any ticking. >> >> I maybe totally wrong, please correct me. Thanks in advance. >> >> Regards >> >> >> On Fri, Jun 7, 2013 at 11:08 PM, Amin Farmahini <amin...@gmail.com>wrote: >> >>> Yes, as far as I know it does not work. >>> O3 to InOrder hack is the way to go. >>> >>> Thanks, >>> Amin >>> >>> >>> On Fri, Jun 7, 2013 at 4:56 PM, Xiangyang Guo <ece...@gmail.com> wrote: >>> >>>> Hi, gem5-users, >>>> >>>> I want to use the InOrder CPU for ARM ISA, but it is not implemented. >>>> in the post, >>>> http://thread.gmane.org/gmane.comp.emulators.m5.users/10970/focus=12145, >>>> there are three patches, I tried, but it doesn't work and the third patch >>>> doesn't finish I think. >>>> >>>> Ashish told me that we can converted O3 to inorder (bypassing register >>>> renaming and using inorder issue and commit). So does this work? Could any >>>> experienced developer tell me if I can follow this way? Thanks in advance >>>> >>>> Regards >>>> >>>> Xiangyang >>>> >>>> _______________________________________________ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > -- > - Korey > -- - Korey
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
