Hello, I think it depends on what memory model one is simulating. If you're using the classic model, than number 2 may define the cache latency.
You can change them, run and see if the config.ini will reflect the changes. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2013/6/19 Mann <[email protected]> > Hi All > > Cache latencies are configurable at 2 places > > 1) src/mem/protocol/**L1Cache.sm > machine(L1Cache, "MSI Directory L1 Cache CMP") > : Sequencer * sequencer, > int l1_request_latency = 2, > int l1_response_latency = 2, > & > 2) configs/common/Caches.py > class L1Cache(BaseCache): > assoc = 2 > block_size = 64 > latency = '1ns' > mshrs = 10 > tgts_per_mshr = 5 > is_top_level = True > > I am not defining anything in running script. > Which one is finally used during simulation ? > > -- > Cheers........... > Mann > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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