Hi All, I want to create a system with 8 cpus, each with private L1 and L2 cache as well as a shared main memory. I am looking at the code in CacheConfig.py under configs/common/.
My question is: I understand I need to make multiple "system.l2" caches. However, do I need to make multiple "system.tol2bus"? or Can I share that one "to level 2" bus between multiple cpus?? Thanks in Advance, Jack _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
