Hi Jack, Yes, simply replicate the "addTwoLevelCache" recipee for each of your CPUs. The toL2bus is no more than a multiplexer to make the L2 cache appear dual-ported (one for the I side and one for the D side).
I hope that helps. Andreas On 26/07/2013 02:19, "Jack Wu" <[email protected]> wrote: >Hi All, > >I want to create a system with 8 cpus, each with private L1 and L2 cache >as well as a shared main memory. I am looking at the code in >CacheConfig.py under configs/common/. > >My question is: > >I understand I need to make multiple "system.l2" caches. However, do I >need to make multiple "system.tol2bus"? or Can I share that one "to level >2" bus between multiple cpus?? > >Thanks in Advance, >Jack >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
