Hi, Zhiguo, First of all, This is just my guess, maybe it is totally wrong.
I think check the ROB/InstQueue free entry in rename stage is reasonable. Because we need to insert the inst into InstQueue/ROB after renaming stage, so before renaming( there is many insts we can rename in a single cycle), we should make sure there is enough space for renamed insts. Otherwise, we should block this thread because the resource limited( structure hazard). And in the dispatch stage, we insert the inst into InstQueue, you could find the relative code in the iew_impl.hh file there is a func "dispatchinsts" and I think this func handle the dispatch stage( gem5 combine all i, e, w into 1 stage) and in this func, we all check if there is free entry in InstQueue by "InstQueue.isfull()". Hope this help. Regards Xiangyang On Tue, Aug 13, 2013 at 11:58 PM, GE ZHIGUO <[email protected]> wrote: > Hi, > > I have a question about O3CPU pipeline in GEM5. > My understanding about the GEM5 O3CPU is that rename stage does not put > instructions > into instruction queue(issue queue) and ROB. Dispatch stage actually does > the > above. So, rename + dispatch in GEM5 is actually the rename stage of > O3CPU. Please correct > me if I am wrong. > As the dispatch stage pushes the instructions into ROB and instruction > Queue, I think that the free entries of ROB and instruction queue should > be checked at > this stage. However, the rename stage in gem5 check the free ROB and > instruction queue size. > I cannot understand this. Can anyone help explain? > > Thanks! > > Zhiguo > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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