Hi, all, As I look through the code of Ruby, I see the Sequencer is connected with the SLICC generated L1 cache controller using a mandatory queue, from which the L1 controller would dequeue. My question is that does ruby have the notion of exclusive read, write and r/w ports? I need to implement a L1 cache with 2 r/w ports. I really appreciate any help from the mailing list. Thanks.
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