After the L1 the second address is block aligned, that is why it differs by the 
low most bits.
Ali

On Oct 7, 2013, at 9:40 PM, Xiangyang Guo <[email protected]> wrote:

> Oops, I'm sorry I made a typo. My question should be  pkt->getAddr() and 
> pkt->req->getPaddr(). Sorry for that. I know the getAddr() will give us the 
> Physical Address,  pkt->req->getPaddr() should of course give us Physical 
> address, but for L2, the two address (several most right bits)are different, 
> but for L1, they are same. Could you help me about this? Thanks a lot.
> 
> 
> On Mon, Oct 7, 2013 at 9:17 PM, Ali Saidi <[email protected]> wrote:
> It's un-usual that pkt->getAddr() and pkt->req->getVaddr() would be the same 
> after translation is complete. The latter will have the virtual address while 
> the latter will have the physical address. As the packet move down the 
> hierarchy it will be further modified to by block aligned, etc.
> 
> Ali
> 
> On Oct 5, 2013, at 11:51 AM, Xiangyang Guo <[email protected]> wrote:
> 
> > Hi,
> >
> > I was using Classic memory and use both pkt->getAddr and 
> > pkt->req->getVaddr() to get the access address. For L1 cache, pkt->getAddr 
> > and pkt->req->getVaddr() give me same address. However, for L2 cache, 
> > pkt->getAddr and pkt->req->getVaddr() give me different address. For 
> > example: 00000140 V.S. 0000017c.
> >
> > I was thinking this is because when we access the L2, we only use the tag 
> > (without considering the index bits and offset bits) to see if it is a hit 
> > or miss. But why the L1 can get the same address? Thanks for your time.
> >
> > Regards
> >
> > Xiangyang
> > _______________________________________________
> > gem5-users mailing list
> > [email protected]
> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 
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