Hi, I was using Classic memory and use both pkt->getAddr and pkt->req->getVaddr() to get the access address. For L1 cache, pkt->getAddr and pkt->req->getVaddr() give me same address. However, for L2 cache, pkt->getAddr and pkt->req->getVaddr() give me different address. For example: 00000140 V.S. 0000017c.
I was thinking this is because when we access the L2, we only use the tag (without considering the index bits and offset bits) to see if it is a hit or miss. But why the L1 can get the same address? Thanks for your time. Regards Xiangyang
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
