Thanks for your quick reply. The gem5 version I use is a bit old, and I will try to test the latest version.
Actually, there is no WriteResp in the mem_comm.trace. Best regards, Yongbing Huang From: [email protected] [mailto:[email protected]] On Behalf Of Andreas Hansson Sent: Wednesday, November 27, 2013 12:54 AM To: gem5 users mailing list Subject: Re: [gem5-users] Usage of CommMonitor I spoke too soon. Could you check your gem5 version? This issue should be resolved since quite a while back. Additionally, is your actual mem_comm.trace containing a WriteResp (you did not mention where you saw this)? Thanks, Andreas From: Andreas Hansson <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Tuesday, 26 November 2013 09:50 To: gem5 users mailing list <[email protected]> Subject: Re: [gem5-users] Usage of CommMonitor Hi, You are right about the "execution" in that the transaction is only put in the trace when the sendTiming call is successful (and thus the port downstream has accepted the packet). This should not present any issues in general. The second problem you mention, with the WriteResp instead of a Req is a bug and I'll fix that. The reason is the order of accepting the packet and putting it in the trace, and the CommMonitor needs to store the request type before passing it on to be on the safe side. It will only cause problems with the monitor directly attached to the memory. Thanks for the pointer. Andreas From: huangyongbing <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Tuesday, 26 November 2013 09:26 To: "[email protected]" <[email protected]> Subject: [gem5-users] Usage of CommMonitor Hi all, I want to use CommMonitor to collect memory trace. I put the CommMonitor between the membus and physmem. The configuration file of CommMonitor is as follows: self.mem_monitor = CommMonitor(trace_file="mem_comm.trace") self.membus.master = self.mem_monitor.slave self.mem_monitor.master = self.physmem.port However, I found two problems according to the memory access trace shown below. dram access: ReadExReq,253755488 comm access: ReadExReq,253755488 dram access: WriteReq,253883392 comm access: WriteResp,253883392 The first problem is that it seems that the DRAM (Physmem) module is executed earlier than the CommMonitor module. The second problem is that the write requests received by CommMonitor are WriteResp requests whereas the requests received by DRAM module are WriteReq requests. So are there any ideas about the problem? Thanks. Best regards, Yongbing Huang -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
